library verilog;
use verilog.vl_types.all;
entity XOR48 is
    port(
        XOR48_Input_A   : in     vl_logic_vector(48 downto 1);
        XOR48_Input_B   : in     vl_logic_vector(48 downto 1);
        XOR48_Select    : in     vl_logic;
        XOR48_Output    : out    vl_logic_vector(48 downto 1);
        XOR48_Finish_Flag: out    vl_logic;
        clk             : in     vl_logic
    );
end XOR48;
